Related Issues (20)
- Undefined parameter used when instantiating bsg_mem_1rw_sync HOT 1
- Syntax errors in generated hard-macro-swapping verilog files when using Python3 HOT 2
- bsg_cache optimization -- don't replay TL instruction if there is no TL instruction HOT 4
- :bug: sync_len_lp is undeclared and undefined in config_snooper.v HOT 2
- bsg_comm_link_master_calib_skip_rom.v is broken HOT 1
- bsg_cache.v ready_o may be yumi_o HOT 2
- Add code for FPGA side of bsg_link HOT 2
- How can we use a basejump_stl component as a top-level module? HOT 9
- bsg_cache_to_test_dram does not support multiple outstanding reads per channel HOT 1
- bsg_nonsynth_dramsim3 failing testbench
- Broken cache testbenches HOT 5
- Release bsg_link FPGA implementation
- Getting Started with BaseJump STL HOT 4
- bsg_dataflow/bsg_fifo_bypass.sv: Port/variable name mismatch HOT 2
- bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv: Variable used before declaration
- SRAM HOT 2
- bsg_dmc_s timing parameters HOT 3
- bsg_dmc: are non-burst write operations supported? HOT 4
- Broken Links HOT 1
- SRAM TSMC 40 nm
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from basejump_stl.