benjstark Goto Github PK

2022w1-lab4-update1

ariane

CS254 project: dual issue of update to date ariane

axi_vip_master

Sample UVM code for axi ram dut

bandpassfilter

FIR band-pass filter using Verilog HDL.

chip-multi-processor-system-based-on-cardinal-bidirectional-ring-network-on-chip

EE577b-Course-Project

dtg-si

Code for "Data-to-text Generation with Style Imitation." [Findings of EMNLP 2020]

face_recognition_matlab

Human Face Recognition System Based on LBP Feature

fpga-nfc

Build an NFC (RFID) card reader using FPGA and simple circuit instead of RFID-specfic chip. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。

gpio_agent

General Purpose I/O agent written in UVM

icdc_lbp

iso_iec_14443a

RTL for the digital part of an ISO 14443-4A tag

nthu-iclab

清華大學 | 積體電路設計實驗 (IC LAB) | 110上

singlecycle-processor-of-risc-v-in-systemverilog

Update the Single Cycle Processor of RISC-V to support 'auipc' and 'xor' instructions

spatio-temporal_handwriting_imitation

Imitating someone's handwriting by converting it to the temporal domain and back again

uvm-apb_ral

This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.

uvm-basics

my UVM training projects

uvm_ral_dma

uvm_verification

Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence