Comments (7)
In my case, the binary includes VFP instructions. It was originally built for STM32F405, which happens to be a supported target for core QEMU, so I sort of assumed that all would work OK. After the configurable_machine.c patch below (to a slightly older version, so it doesn't apply directly to the current development branch) it seemed to work for my needs.
499c499
< if (!strcmp(cpu_type, "cortex-m3")) {
---
> if (!strcmp(cpu_type, "cortex-m3") || !strcmp(cpu_type, "cortex-m4")) {
508c508,512
< qdev_prop_set_string(dstate, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
---
> if (!strcmp(cpu_type, "cortex-m3")) {
> qdev_prop_set_string(dstate, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
> } else {
> qdev_prop_set_string(dstate, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
> }
from avatar2.
Yes but QEmu would still be able to run those firmwares, as long as it provides a superset implementing all operations present in the firmware.
It is not an exact replication but in most cases it should be sufficient.
from avatar2.
The error message is indeed lacking clarity, but IIRC the support for M4 isn't complete. Is that correct @mariusmue @rawsample ?
from avatar2.
Hi,
Indeed the error message is not clear.
If your binary doesn't make usage of cortex-m4 additional features such as FPU, DSP, etc., you should be able to use the cortex-m3 core for emulation.
Simply changing the option to cortex-m4 would not solve the issue because avatar2 python part has no knowledge of it: https://github.com/avatartwo/avatar2/blob/main/avatar2/archs/arm.py
from avatar2.
I discussed with a student here (Florian) he seem to have a fix for that and will come back here soon about it.
from avatar2.
On the QEMU side my idea is pretty much what @GregIthaca proposes, QEMU has support for the full cortex-m4 with FPU and DSP.
On the python side a quickfix would be to add this architecture in arm.py
:
class ARM_CORTEX_M4(ARM_CORTEX_M3):
cpu_model = 'cortex-m4'
Although this will NOT transfer the state of the FPU, it will transfer all the other state as the M4 and M3 overlap in most things, just the FPU adds new registers to the M4.
Although, the FPU is an optional feature, we might want to have 2 separate architectures, one with and one without the FPU registers?
from avatar2.
Yes, unfortunately it's potentially even more complicated than that, since some core version could theoretically implement only portions of the VFP. But based on the contents of the QEMU cpu->isar.mvfr0 = 0x10110021
(here) QEMU is going to assume that M4=VFPv2.
from avatar2.
Related Issues (20)
- RemoteMemoryRead failed: Failed to read memory!
- Exception: GDBProtocol was unable to connect HOT 4
- Installer has invalid references to GitHub repos HOT 2
- Is it possible to dynamically analyse the firmware of a ESP32 just with the default avatar2 tools? HOT 4
- avatar2/handbook/0x03_memory.md/Avatar² Peripheral Emulation Ranges HOT 20
- AvatarPeripheral with x86 target HOT 5
- A naive question: what means rcc dump HOT 1
- Stuck when openocd_target try to wait HOT 2
- RecursionError: maximum recursion depth exceeded in comparison HOT 2
- geting to halt state when transfer state from QemuTarget to gdbTarget
- How to deal with interrupt (NVIC) HOT 2
- avatar.CRITICAL | No Memory range specified at 0x400008
- questions regarding gdbstub, SerialICE and avatar[one] HOT 2
- Failure to check for qemu failure at startup HOT 2
- query: per-opcode filters/logging? HOT 2
- AvatarPeripheral: pci/pcie devices
- How to implement an Android Emulator target? HOT 7
- avatar2/handbook/0x03_memory.md Qemu Properties dict possible types and values details HOT 1
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from avatar2.