Comments (2)
Hi @sainikitha79 Thanks for the questions..
- arm_nn_requantize() is a requantization step from 32 bit input into 8 bits. For e.g when you do Multiply Accumulates for a int8 convolution operation, the result is in 32 bits . requantization gets it back to 8 bits and it follows the TensorFlow Lite specification for int8 quantization.
- 2 and 3 are activation functions for sigmoid and tanh. Those tables are the integer pre-calculated sigmoid values.
- vmaxq is an Arm Helium Technology intrinsic. https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:@navigationhierarchiessimdisa=[Helium]&q=vmaxq[_s32] . It is applicable for e.g on the latest Arm Cortex-M55 processor with M-Profile Vector Extension(MVE). It performs max of two values in their corresponding lanes of the q or vector register.
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Thank you so much for your explanation.
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Related Issues (20)
- missing arm_s8_to_s16_unordered_with_offset.c when I included the pack HOT 3
- Output diff for new lstm-operator
- Confusing doc on `arm_nn_requantize`
- MVE Conv 1 x N does not handle all configurations HOT 1
- Unit tests fails to build with -O0
- Possible undefined behavior for `arm_nn_requantize` when compiling with `CMSIS_NN_USE_SINGLE_ROUNDING` HOT 9
- Inconsistency of CMSIS-NN Quantization Method(Q-format) with ARM Documentation HOT 4
- Inconsistency of CMSIS-NN Quantization Method(Q-format) with ARM Documentation HOT 2
- No MVE support Conv2D int16
- arm_elementwise_add_s8 does not work properly for a Residual Architecture HOT 7
- IAR compiler issues HOT 1
- Is there a roadmap? HOT 3
- Does the MVEI version of CMSIS NN have implementations of q15 and q7? HOT 1
- Vector of variable length used in arm_convolve_1x1_s8_fast HOT 1
- Documentation warning HOT 1
- What does CMSIS exactly refer to? HOT 1
- Occur an ASM error when compiling arm_nn_mat_mul_core_4x_s8 HOT 11
- reserved identifier violation HOT 6
- Is there some easy to get started guide? HOT 1
- Include/Internal/arm_nn_compiler.h: undefined __ARM_FEATURE_MVE HOT 1
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