Can't collect some events on Xeon E5-2630 v3 about pmu-tools HOT 3 CLOSED

$] cat /proc/cpuinfo
processor       : 15
vendor_id       : GenuineIntel
cpu family      : 6
model           : 63
model name      : Intel(R) Xeon(R) CPU E5-2630 v3 @ 2.40GHz
stepping        : 2
microcode       : 0x23
cpu MHz         : 2399.891
cache size      : 20480 KB
physical id     : 1
siblings        : 8
core id         : 7
cpu cores       : 8
apicid          : 30
initial apicid  : 30
fpu             : yes
fpu_exception   : yes
cpuid level     : 15
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer xsave avx f16c rdrand lahf_lm abm arat epb xsaveopt pln pts dtherm tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid
bogomips        : 4801.05
clflush size    : 64
cache_alignment : 64
address sizes   : 46 bits physical, 48 bits virtual
power management:

$] python ~/pmu-tools/toplev.py -l5 th imc.lua
Will measure complete system.
Using level 5.
warning: removing Core_Bound Ports_Utilization L1_Bound 0_Ports_Utilized
Memory_Bound L2_Bound due to unsupported events in kernel:
CYCLE_ACTIVITY.CYCLES_NO_EXECUTE CYCLE_ACTIVITY.STALLS_L1D_PENDING
Use --force-events to override (may result in wrong measurements)
perf stat -x, -e 'task-clock,{cpu/event=0x9c,umask=0x1/,cpu/event=0xc3,umask=0x1,edge=1,cmask=1/,cpu/event=0xc2,umask=0x2/,cpu/event=0xe,umask=0x1/,cycles,cpu/event=0x79,umask=0x30/,cpu/event=0x9c,umask=0x1,cmask=4/,cpu/event=0x
c5,umask=0x0/,cpu/event=0xd,umask=0x3,cmask=1/,instructions},{cpu/event=0x80,umask=0x4/,cpu/event=0xab,umask=0x2/,cpu/event=0x85,umask=0x60/,cpu/event=0x87,umask=0x1/,cpu/event=0x14,umask=0x2/,cpu/event=0x79,umask=0x30,edge=1,cm
ask=1/,cpu/event=0xc1,umask=0x40/,cycles,cpu/event=0x85,umask=0x10/},{cpu/event=0xa8,umask=0x1,cmask=1/,cpu/event=0xa2,umask=0x8/,cpu/event=0x79,umask=0x24,cmask=4/,cpu/event=0xa3,umask=0x6,cmask=6/,cpu/event=0x79,umask=0x24,cma
sk=1/,cpu/event=0x79,umask=0x18,cmask=1/,cpu/event=0xa8,umask=0x1,cmask=4/,cycles,cpu/event=0x79,umask=0x18,cmask=4/},{cpu/event=0xa3,umask=0x5,cmask=5/,cpu/event=0xd1,umask=0x4/,cpu/event=0xd1,umask=0x20/,cycles},{cpu/event=0x8
0,umask=0x4/,cpu/event=0xc3,umask=0x1,edge=1,cmask=1/,cpu/event=0xe6,umask=0x1f/,cpu/event=0x5e,umask=0x1,edge=1,inv=1,cmask=1/,cpu/event=0x85,umask=0x60/,cpu/event=0xc5,umask=0x0/,cycles,cpu/event=0x5e,umask=0x1/,cpu/event=0x85
,umask=0x10/},{cpu/event=0x7,umask=0x1/,cpu/event=0xd1,umask=0x4/,cpu/event=0xd0,umask=0x42/,cpu/event=0x3,umask=0x2/,cpu/event=0xb1,umask=0x2,cmask=3/,cpu/event=0x60,umask=0x1,cmask=6/,cycles,cpu/event=0xd2,umask=0x2/,cpu/event
=0xb2,umask=0x1/},{cpu/event=0x8,umask=0x60/,cpu/event=0x49,umask=0x60/,cpu/event=0xd2,umask=0x4/,cpu/event=0xd2,umask=0x1/,cpu/event=0x49,umask=0x10/,cpu/event=0x8,umask=0x10/,cpu/event=0x60,umask=0x1,cmask=1/,cycles,cpu/event=
0x60,umask=0x1,cmask=6/},{cpu/event=0xb1,umask=0x2,cmask=1/,cpu/event=0xd1,umask=0x40/,cpu/event=0xd1,umask=0x8/,cpu/event=0xb1,umask=0x2,cmask=2/,cpu/event=0xb1,umask=0x2,cmask=3/,cpu/event=0x48,umask=0x2,cmask=1/,cycles,cpu/ev
ent=0x3,umask=0x8/,cpu/event=0x48,umask=0x1/},{cpu/event=0xd3,umask=0x1/,cpu/event=0xa1,umask=0x10/,cpu/event=0xa1,umask=0x8/,cpu/event=0xa1,umask=0x2/,cpu/event=0xa1,umask=0x1/,cpu/event=0xa1,umask=0x20/,cpu/event=0xa1,umask=0x
4/,cycles,cpu/event=0xd3,umask=0x4/},{cpu/event=0xa1,umask=0x40/,cpu/event=0xd3,umask=0x20/,cycles,cpu/event=0xa1,umask=0x80/,cpu/event=0xd3,umask=0x10/}' -A -a th imc.lua

28 events not supported
0     BE      Backend_Bound:                70.51%
        This category reflects slots where no uops are being
        delivered due to a lack of required resources for accepting
        more uops in the Backend of the pipeline...
0             CPU utilization:        0.88 CPUs
        Number of CPUs used...
1     BE      Backend_Bound:                70.43%
1             CPU utilization:        0.88 CPUs
10    BE      Backend_Bound:                67.95%
10            CPU utilization:        0.88 CPUs
11    BE      Backend_Bound:                66.47%
11            CPU utilization:        0.88 CPUs
12    BE      Backend_Bound:                68.04%
12            CPU utilization:        0.88 CPUs
13    BE      Backend_Bound:                68.09%
13            CPU utilization:        0.88 CPUs
14    BE      Backend_Bound:                67.19%
14            CPU utilization:        0.88 CPUs
15    BE      Backend_Bound:                69.92%
15            CPU utilization:        0.88 CPUs
2     BE      Backend_Bound:                70.54%
2             CPU utilization:        0.88 CPUs
3     BE      Backend_Bound:                71.07%
3             CPU utilization:        0.88 CPUs
4     BE      Backend_Bound:                70.48%
4             CPU utilization:        0.88 CPUs
5     BE      Backend_Bound:                70.52%
5             CPU utilization:        0.88 CPUs
6     BE      Backend_Bound:                70.57%
6             CPU utilization:        0.88 CPUs
7     BE      Backend_Bound:                70.39%
7             CPU utilization:        0.88 CPUs
8     BE      Backend_Bound:                67.79%
8             CPU utilization:        0.88 CPUs
9     BE      Backend_Bound:                67.20%
9             CPU utilization:        0.88 CPUs