Comments (4)
Does cmask=12 work correctly too?
Yes it looks like a bug in the event list. I'll report it.
For now you can patch the event list manually in ~/.cache/pmu-events/GenuineIntel-6-3F.json
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It turned out to be a kernel bug. 12 is the correct cmask, but the kernel would schedule it on the wrong counter.
Kernel patch (cut'n'pasted, may need to be applied manually)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 9f1dd18..35d9f5a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -212,11 +212,11 @@ static struct event_constraint intel_hsw_event_constraints[] = {
INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST /
INTEL_EVENT_CONSTRAINT(0xcd, 0x8), / MEM_TRANS_RETIRED.LOAD_LATENCY /
/ CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
-
INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
-
INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /\* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
-
INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
-
INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /\* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
-
INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
-
};
INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), EVENT_CONSTRAINT_END
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That didn't work well because MarkDown. Here's the patch
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Thanks! I just tried with a patched kernel. perf now reports the numbers correctly.
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