Comments (1)
nmigen-issue-migration
commented on September 13, 2024
Thursday Jan 17, 2019 at 20:50 GMT
Codecov Report
Merging #26 into master will not change coverage.
The diff coverage isn/a.
@@ Coverage Diff @@
## master #26 +/- ##
=======================================
Coverage 81.85% 81.85%
=======================================
Files 22 22
Lines 3710 3710
Branches 745 745
=======================================
Hits 3037 3037
Misses 603 603
Partials 70 70Continue to review full report at Codecov.
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Related Issues (20)
- Tracking issue for RFC 58: Core support for `ValueCastable` formatting
- Tracking issue for RFC 61: Minimal stream interface
- `execute_local_docker()` does not forward SIGINT/ctrl+c to docker subprocess HOT 4
- Bit width of `Signal(range(1))` HOT 2
- verilog output error: syntax error in left side of continuous assignment. HOT 2
- Wrong verilog for combinatorial module HOT 2
- pysim LHS compiler miscompiles `Slice` of `SwitchValue`
- `Signal.like` is not fully functional with `ShapeCastable`-based signals
- Tracking issue for RFC 63: Remove `amaranth.lib.coding`
- Tracking issue for RFC 65: Special formatting for structures and enums
- Question: Combinational vs Combinatorial HOT 7
- Pyright errors on `m.[If/Elif/Else]`: No `__enter__` or `__exit__` HOT 1
- Unclear error message on `m.domains.cd_tx = ClockDomain()`
- Can't emit Verilog/RTLIL with Signature array members HOT 1
- Add `AMDPlatform`, aliasing `XilinxPlatform`
- Make `Module` explode if you try to modify it after it's elaborated
- Extremely slow Verilog generation HOT 5
- Pysim should reject async generators
- Constraint generation from platform resource with `DiffPairs` of type LVDS incorrect. HOT 1
- Adding simulator processes after starting the simulation is not well-defined HOT 2
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from amaranth.