Comments (1)
Denominating from 0.3 because this issue requires #228.
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Related Issues (20)
- Kill `Value._lhs_signals` and `Value._rhs_signals`
- Signals with private names HOT 4
- Roadmap to Amaranth 0.5 HOT 1
- Fix failing uploads to TestPyPI from CI HOT 1
- Do something with `Value.implies` HOT 2
- Tracking issue for RFC 62: The `MemoryData` class. HOT 1
- Tracking issue for RFC 59: Get rid of upwards propagation of clock domains
- Tracking issue for RFC 58: Core support for `ValueCastable` formatting
- Tracking issue for RFC 61: Minimal stream interface
- `execute_local_docker()` does not forward SIGINT/ctrl+c to docker subprocess HOT 4
- Bit width of `Signal(range(1))` HOT 2
- verilog output error: syntax error in left side of continuous assignment. HOT 2
- Wrong verilog for combinatorial module HOT 2
- pysim LHS compiler miscompiles `Slice` of `SwitchValue`
- `Signal.like` is not fully functional with `ShapeCastable`-based signals
- Tracking issue for RFC 63: Remove `amaranth.lib.coding`
- Tracking issue for RFC 65: Special formatting for structures and enums
- Question: Combinational vs Combinatorial HOT 7
- Pyright errors on `m.[If/Elif/Else]`: No `__enter__` or `__exit__` HOT 1
- Unclear error message on `m.domains.cd_tx = ClockDomain()`
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