Comments (2)
Declare 8 bit reg m_axi_awlen_reg
, initialize it to zero, declare 8 bit reg m_axi_awlen_next
, initialize it to X
.
from verilog-axi.
Oh.... thanks! I assumed it was a declaration of a single register, but I see now that it declares two. Got it. thanks! :)
from verilog-axi.
Related Issues (20)
- About priority_encoder HOT 4
- AXI Reset Signal
- AXI Lite interconnect in N to 1 configuration HOT 2
- axi_interconnect Synthesis HOT 1
- Why assume packet smaller than max burst size when AXI_MAX_BURST_SIZE >=4096? HOT 10
- awready and wready set high in master without slave value
- I met a question about simulation, please some one help me? HOT 2
- about AXI_VFIFO HOT 3
- Q: Do axi_dma_rd and axi_dma_wr support out of order transactions? HOT 2
- about axi_ram design specification
- Q: is there any component for read data out of standard ram/fifo and then transfer the data to axi master HOT 4
- Will unprocessed awvalid signals be stored in AXI Crossbar? HOT 6
- Axi DMA consistently returns DECERR HOT 6
- Timing issues with `axi_dma_wr`
- About width missmatch HOT 2
- about tb HOT 1
- About the solution for deadlocks HOT 14
- Failed to run test for AXI RAM with DATA_WIDTH=64 and ADDR=64 HOT 4
- AXI_Register hangs when SIM=verilator HOT 3
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