akinglw Goto Github PK
Type: User
akinglw's Projects
amba-axi4-lite
Master and Slave made using AMBA AXI4 Lite protocol.
axi
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
axi_bfm
AXI4 BFM in Verilog
basic_verilog
Must-have verilog systemverilog modules
cocotbext-axi
AXI interface modules for Cocotb
cocotbext-pcie
PCI express simulation framework for Cocotb
corundum
Open source FPGA-based NIC and platform for in-network compute
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
implementation-of-amba-axi3-protocol
Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System Verilog simulator and the Mentor Graphics Veloce hardware emulator.
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
riffa
The RIFFA development repository
system-bus-design-verilog
This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
tree-core-ide
:deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
verilog-axi
Verilog AXI components
verilog-ethernet
Verilog Ethernet components for FPGA implementation
verilog-pcie
Verilog PCI express components
wujian100_open
IC design and development should be faster，simpler and more reliable
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