Comments (1)
I've added the license for the implementation in dc12eed.
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Related Issues (17)
- Double underscores are illegal in VHDL HOT 1
- Non-stream signal reversibility
- Tydi TODO
- Splitting LogicalStreamType into non-nested streams should result in a new type HOT 1
- Logical stream iterators HOT 1
- Improve generator code path
- Add concrete type definitions
- A Tydi language HOT 1
- Can't compile due to type mismatch
- Union semantics and variant enumeration order for tag bits HOT 1
- Flattening when both streams have user and/or keep properties HOT 1
- Requirements for "last" signalling conflict for Streams with lower complexities and multiple element lanes
- It is not clear whether "stai" and "endi" signals are significant when "strb" is low.
- Transferring empty outer lists at lower complexities
- Inconsistency: Strobe only encodes individual lane validity at Cā„8
- Requirements when C<5, Dimensionality = 0 and Throughput > 1
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