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2-level-optimizer-espresso

Espresso Assignment

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64-bit-full-adder-design-in-vivado

IP Based 64-Bit Full Adder Design in Xilinx Vivado, involving Verifications using Virtual I/O and Integrated Logic Analyzer

advanced-tic-tac-toe

Develop an advanced version of Tic Tac Toe game that incorporates user authentication, personalized game history, and an intelligent (Artificial Intelligent) AI opponent.

algebraic-division-algorithm

In the context of Multilevel Synthesis (MLS) used in digital circuit design, algebraic division plays a significant role, particularly in factoring and optimizing logic functions represented in Boolean algebra.

asterisctechnocrat_internship

Asterisc Technocrats' tasks: Student Management System, PAYROLL Management System, INVENTORY Management System, CAFE Management System

bootloader-executing-c-program

A simple bootloader in assembly that loads and executes a c program.

codsoftsep

CodSoft's Internship with 3 main tasks: TO-DO LIST A To-Do List application, Design a simple calculator, PASSWORD GENERATOR

compseq

Design more than 30 Compational&Sequential Circuits VHDL & Verilog (most of them design their TestBench for functional correctness testing) using ModelSim Software.

digital-ic-design-iti-2024

Digital IC Design Course [STILL CONTINUOUS]

highspeedlowvthmosanalogdesign

Three main tasks, each focusing on the design and analysis of different aspects of MOS transistors using a UMC 0.13µm technology

logic-equivalence-checking-with-bdds

An Assignment in VLSI CAD Part I: Logic Course under supervision of Rob A. Rutenbar, Adjunct Professor

logic-equivalence-checking-with-sat

An Assignment 2 in VLSI CAD Part I: Logic Course under supervision of Rob A. Rutenbar, Adjunct Professor

maze-solver-car

Maze solver line follower car

pwm-design

Implements a Pulse Width Modulation (PWM) module using a Finite State Machine (FSM) in Verilog.

rtos-communicating-tasks-project

An Embedded Systems project focused on Real-Time Operating System (RTOS) concepts using FreeRTOS.

securitysystemproject

Security System Project is integration between Embadded Systems and PCB Design

serial-peripheral-interface

The project involves designing a Serial Peripheral Interface (SPI) module in Verilog for communication between a master and multiple slave devices involving verification using simple testbench and hardware debugging using VIO, ILA in Vivado

serious-bdds

Focused on network repair applications using KBDD scripts

smart-garage-project

Smart Garage project

smarthomeautomation

Smart Home Automation based on Arduino Microcontroller realizing the concept of Renewable Energy in smart homes by using renewable energy source as solar cell & wind power

spartan6dsp_alsu

uart-protocol

A hardware communication protocol that uses serial communication to exchange data between devices implemented in Verilog HDL with randomized testbench to ensure functional verification, synthesized in VIVADO, Implemented in Nexys4 DDR (xc7a100tcsg324-1) FPGA

unate-recursive-complement

Unate Recursive Paradigm (URP) idea to determine tautology for a Boolean equation available as a SOP cube list, represented in Positional Cube Notation (PCN). It turns out that many common Boolean computations can be done using URP ideas.

verilog-i2c-master

Single Port RAM and I2C EEPROM Controller