2cc2ic Goto Github PK
Name: zhanghq
Type: User
Bio: FPGAer SOCer ICer
Location: Shanghai Pudong New Area
Name: zhanghq
Type: User
Bio: FPGAer SOCer ICer
Location: Shanghai Pudong New Area
Build an open source, extremely simple DMA.
This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to build a DMA based image data cache transmission system. On this basis, Verilog HDL was used to design the axi4-stream interface based IP core for image processing, so as to build a high real-time moving target detection system. In our design, we focus on the optimization of processing pipeline, improve the traditional frame difference method, and achieve the optimization goal of saving logical resources through the accumulation compression and reconstruction expansion of cached background frames.
Design a complete IP, including AXI data reading, pipeline algorithm optimization, and AXI output data write
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