A topological loop is generated after using async2sync about yosys HOT 2 OPEN

Can you try on current master? There was a patch that improved loop detection and got rid of some false positives not too long ago.

Edit: I can't reproduce this on version 0.40+25. I get a different error:

...
9. Executing SIM pass (simulate the circuit).
Simulating cycle 0.
ERROR: Unsupported cell type: $check (or1200_top.$assert$or1200_dut_new.v:10001$2062)

from yosys.

@rowanG077
After downloading the new version of Yosys (Yosys 0.41+108), I still cannot solve this problem. No logic loop is produced before the async2sync, while 2 logic loops are generated after executing the async2sync.

The different error is because the async2sync needs to be executed before the sim. The attachment is the new version, I have moved the command async2sync before the sim:
reproduce.tar.gz

from yosys.