AIM:
To implement 4 Bit Ripple Counter using verilog and validating their functionality using their functional tables
SOFTWARE REQUIRED:
Quartus prime
THEORY
4 Bit Ripple Counter
A binary ripple counter consists of a series connection of complementing flip-flops (T or JK type), with the output of each flip-flop connected to the Clock Pulse input of the next higher-order flip-flop. The flip-flop holding the least significant bit receives the incoming count pulses. The diagram of a 4-bit binary ripple counter is shown in Fig. below.
In timing diagram Q0 is changing as soon as the negative edge of clock pulse is encountered, Q1 is changing when negative edge of Q0 is encountered(because Q0 is like clock pulse for second flip flop) and so on.
Procedure
- Increment count on each positive edge of the clock.
- Reset count to zero when it reaches 15.
- Generate clock signal (clk).
- Instantiate the RippleCounter module.
- Conduct functional testing by displaying the count at each clock cycle for 16 cycles.
PROGRAM
/* Program for 4 Bit Ripple Counter and verify its truth table in quartus using Verilog programming. Name: NITHIYANANDAN N RegisterNumber:212222230099 */
module exp12(
input wire clk, // Clock input
output reg [3:0] count // 4-bit counter output
);
// Counter logic
always @(posedge clk) begin
if (count == 4'b1111) // Reset when count reaches 15
count <= 4'b0000;
else
count <= count + 1; // Increment count
end
endmodule
// Testbench
module RippleCounter_tb;
// Inputs
reg clk;
// Outputs
wire [3:0] count;
// Instantiate the counter
RippleCounter uut(
.clk(clk),
.count(count)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // Toggle clock every 5 time units
end
// Stimulus
initial begin
// Wait for a few clock cycles
#10;
// Display header
$display("Time | Count");
$display("-----------------");
// Functional table testing
// Increment count 16 times and display the count
repeat (16) begin
#5; // Wait for one clock cycle
$display("%4d | %b", $time, count);
end
// End simulation
$finish;
end
endmodule
RTL LOGIC FOR 4 Bit Ripple Counter
TIMING DIGRAMS FOR 4 Bit Ripple Counter
RESULTS Thus the program executed succesfully.