AIM:
To implement the given logic function verify its operation in Quartus using Verilog programming.
F1= A’B’C’D’+AC’D’+B’CD’+A’BCD+BC’D
F2=xy’z+x’y’z+w’xy+wx’y+wxy
Equipment Required:
Hardware – PCs, Cyclone II , USB flasher
Software – Quartus prime
Theory
Logic Diagram
Procedure
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Type the program in Quartus software.
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Compile and run the program.
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Generate the RTL schematic and save the logic diagram.
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Create nodes for inputs and outputs to generate the timing diagram.
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For different input combinations generate the timing diagram.
Program: Program to implement the given logic function and to verify its operations in quartus using Verilog programming.
Name: Kurapati Vishnu Vardhan Reddy
RegisterNumber: 212223040103
module Boolean_min(A,B,C,D,W,X,Y,Z,F1,F2);
input A,B,C,D,W,X,Y,Z;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10;
output F1,F2;
assign x1=(~A)&(~B)&(~C)&(~D);
assign x2=(A)&(~C)&(~D);
assign x3=(~B)&(C)&(~D);
assign x4=(~A)&(B)&(C)&(D);
assign x5=(B)&(~C)&(D);
assign x6=(X)&(~Y)&(Z);
assign x7=(~X)&(~Y)&(Z);
assign x8=(~W)&(X)&(Y);
assign x9=(W)&(~X)&(Y);
assign x10=(W)&(X)&(Y);
assign F1=x1|x2|x3|x4|x5;
assign F2=x6|x7|x8|x9|x10;
endmodule
RTL realization
Output:
Result:
Thus the given logic functions are implemented using and their operations are verified using Verilog programming.