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Hey! Nice to See You 👋

I'm Mingjun Jiang

  • ⭐ A Graduate FPGA Developer at Optiver
  • ✨ Graduated from SJTU with a master's degree in Intergrated Circuit Engineering
  • 🔭 Interested in Digital IC Design/Verification and FPGA Heterogeneous Computing
  • 🌱 Focus on CPU-FPGA Co-design to accelerate domain specific algorithm including Machine Learning, Bioinformatics and High Frequency Trading
  • 📫 Connect with Me: [email protected]

Tech Stack 🛠

Verilog SystemVerilog C/C++ UVM OpenCL CUDA OpenVINO Linux

Open Source Project

  • AXI Ethernet UVM : A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  • OpenVINO Mobilenetv2_SSD MultiNCS2 : Accelerate MobileNetV2-SSD on Intel CPU and Neural Compute Stick2 based on OpenVINO
  • Binocular Depth Estimation : Calculate depth of field using different cost functions(SAD/NCC/SHD) based on MATLAB

Currently Working on

  • Working at Optiver as Graduate FPGA Developer
  • Learning Computer Architecture and Computer Network
  • Learning IC Design and Verification
  • Learning Software Knowledge and Tarding Knowledge
  • ......

kkenshin's Projects

axi-ethernet-uvm icon axi-ethernet-uvm

A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM

cutlass icon cutlass

CUDA Templates for Linear Algebra Subroutines

googletest icon googletest

GoogleTest - Google Testing and Mocking Framework

hdlbits-result icon hdlbits-result

Record verilog answers to some questions in HDLBits (mainly FSM)

zipcpu icon zipcpu

A small, light weight, RISC CPU soft core

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