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32-verilog-mini-projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

a-single-path-delay-32-point-fft-processor

A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.

advanced-physical-design-laboratory

advanced-physical-design-openlane-sky130

advanced-physical-design-using-openlane-sky130-workshop

advanced-physical-design-workshop-using-openlane-sky130

advanced_physical_design_using_openlane_sky130_workshop

asciidocfx

Asciidoc Editor and Toolchain written with JavaFX 16 (Build PDF, Epub, Mobi and HTML books, documents and slides)

avsddac_3v3_sky130_v2

badboy1307

Config files for my GitHub profile.

cad-algorithms-vlsi-design

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

circuit-design-simulation-and-analysis-esim-skywater-130nm

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

efabless-contest-

fft_chipdesign

A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.

jenef15

Config files for my GitHub profile.

openlane-skywater130-workshop

This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop helps to familiarise with the efabless OpenLANE VLSI design flow RTL2GDS and the Skywater 130nm PDK.

physical-design-with-openlane-using-sky130-pdk

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

rtldesignusingverilogwithsky130technology

RTL design using Verilog with SKY130 Technology. This is a 5-Day online workshop conducted by VLSI System Design, Banglore from 26th-30th May 2021. Learn basics of digital design using Verilog language, various RTL coding styles, typical synthesis problems faced by the industry, and how to solve them in Verilog.

simanneal

Python module for Simulated Annealing optimization

sky130_rtl_synth_workshop

sky130rtldesignandsynthesisworkshop

skywater-openlane-physical-design

This is the documentation of the 5-day journey in the "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design (VSD)

t13x

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

vsddevboard_v0

vsdmixedsignalflow

This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.

vsdsram_sky130

vsdstdcelldesign

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.