Name: Konsta M
Type: User
Company: Vaasan Yliopisto / University of Vaasa
Bio: SW Developer / FPGA Engineer, M.Sc. in Electrical Engineering. Mainly Java & C# stuff in Github. Also FPGA for now: (System)Verilog, VHDL.
Location: Vaasa, Finland
Blog: https://stackoverflow.com/users/8063451/am9417
Konsta M's Projects
Extensions for VisualStudio UnitTest's Assert class to simplify e.g. testing of view models.
Java-based simple dynamic DNS client
FPGA Client
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/